摘  要：脉冲控制需要运动控制系统根据输入的速度值，对输出的控制脉冲进行均匀分配，以保证电机转速的稳定。在对比了一种脉冲均匀分配算法后，该文采用了直接数字频率合成（DDS）算法，在运动控制系统的FPGA芯片中用Verilog HDL语言完成了脉冲发生器的设计。该脉冲发生器具有速度与位置两种控制模式，并可以根据电机驱动器的工作模式输出4种不同的脉冲。测试表明该发生器的输出脉冲均匀稳定，分辨率高，频率范围完全覆盖宽，完全可以满足步进控制的需求。同时根据脉冲发生与接收测试的结果，对运动控制系统中的相关问题进行了分析研究。
关键词：步进控制;FPGA;DDS算法;脉冲发生

Abstract: In the background of step control, to ensure stable running of motor, output control pulses should be assigned uniformly by the motion control card based on input velocity. After comparing with an algorithm for uniform pulse assignment, direct digital frequency synthesis (DDS) algorithm was adopted to design the pulse generator in FPGA using Verilog HDL. This pulse generator has velocity and position control mode, could provide 4 kinds of pulse depended on the mode of motor driver. The output pulse was tested to be uniform and stable with high resolution. And the wide range of frequency could fulfill the requirement for step control. Relative problems in the motion control system were also analyzed based on the result of test.
Key Words: Step control; FPGA; DDS algorithm; Pulse generate